Today's ICs may contain many embedded 1149.1 TAP domains. Some of these TAP domains are associated with intellectual property (IP) core circuits within the IC, and serve as access interfaces to test, debug, emulation, and programming circuitry within the IP cores. Other TAP domains may exist in the IC which are not associated with cores but rather to circuitry in the IC external of the cores. Further, the IC itself will typically contain a TAP domain dedicated for operating the boundary scan register associated with the input and output terminals of the ICs, according to IEEE std 1149.1.
FIG. 1 illustrates an example architecture for selecting Tap domains within an IC 102. This architecture is described in detail in referenced U.S. Pat. No. 7,058,862. In the architecture, Tap domains 1-3 (TD1-TD3) are shown to exist between input linking circuitry 108 and output linking circuitry 110 of circuit block 106. While three Tap domains TD1-TD3 are shown in this example, any number of Tap domains may exist between the input and output linking circuitry. Each Tap domain TD1-TD3 has a Test Data Input (TDI) 112 coupled to the input linking circuitry 108, a Test Data Output (TDO) 114 coupled to the input linking circuitry 108 and output linking circuitry 110, and a control interface 116 consisting of Test Clock (TCK), Test Mode Select (TMS), and a Test Reset (TRST) signals coupled to the input linking circuitry. The input linking circuitry 108 is coupled to a TDI input 122 to the IC and to TCK, TMS, and TRST control inputs 124 to the IC. The input and output linking circuits 108 and 110 are described in detail in the above reference application and serve basically as multiplexing circuits that selectively link Tap domains together serially between the IC's TDI 122 and TDO 120 leads. The input linking circuitry also couples the IC's TCK and TMS inputs to the selected Tap domains control inputs 116 so they can receive control to operate when coupled to the IC's TDI 122 and TDO 120 leads. To be compliant to the IEEE 1149.1 boundary scan standard, the data on the IC's TDI 122 lead is clocked into the architecture on the rising edge of TCK 124 and the data on the IC's TDO 120 lead is clocked from the architecture on the falling edge of TCK 124. While not shown, circuitry is assumed to exist on the TDO 120 lead to allow data from the architecture to be clocked out on the falling edge of TCK.
The Tap Domain Selection (TDS) circuit 104 is coupled to the IC's TDO output via serial path 120, to the output linking circuitry 110 via serial path 118, to the input and output linking circuits 108 and 110 via control bus 126, and potentially to other circuits in the IC via control bus 126. The TDS circuit is also coupled to the IC's TCK, TMS, and TRST input leads 124. In response to control bus 126 input from TDS 104, the input and output linking circuitry may serially connect any one or combination of Tap domains TD1-TD3 between the IC's TDI 122 and serial path 118 to the TDS for access. For example, Tap domain connections may be made between the IC's TDI 122 and serial path 118 that includes; TD1 only, TD2 only, TD3 only, TD1 and TD2, TD1 and TD3, TD1 and TD2 and TD3, or TD2 and TD3. As seen, the TDS circuit remains in the scan path, along with the selected Tap domains, to complete the serial connection path between the IC's TDI 122 and TDO 120 leads. In the referenced U.S. Pat. No. 7,058,862, the TDS was referred to as a Tap Linking Module (TLM). The TDS of this application is slightly different from the TLM, and so it has been named differently. With the exception of TDS 104, the architecture of FIG. 1 is like that described in U.S. Pat. No. 7,058,862.
FIG. 2 illustrates a simple example of an IEEE 1149.1 Tap domain architecture 202. The Tap domain architecture includes a Tap controller 204, an instruction register (IR) 206, at least one data register (DR) 208, and multiplexer circuitry 210. Each of the Tap domains TD1-TD3 and the TDS 104 are based on Tap domain architecture 202. The above mentioned difference between the TDS and TLM was that the TLM did not necessarily require a DR in the Tap domain architecture, a direct connection between TDI and TDO could be used in place of a DR in the TLM. It should be understood however, that the TLM could be substituted for the TDS if desired to make to the two Tap domain architectures be the same. In response to TCK and TMS control inputs to Tap controller 204, the Tap controller outputs control to capture data into and shift data through either the IR 206 from TDI to TDO or a selected DR 208 from TDI to TDO. The data shifted into IR 206 is updated and output on bus 214, and the data shifted into a DR is updated and output on bus 212. DR 208 may also capture data from bus 212 and IR 206 may capture data from bus 214. Buses 212 and 214 form bus 126 of TDS 104 in FIG. 1. In response to a TRST input to the Tap controller 204, the TAP controller, IR and DR are reset to known states. The structure and operation of IEEE 1149.1 Tap domain architectures like that of FIG. 2 are well known.
FIG. 3 illustrates in more detail the structure 302 of the IR 206 and DR 204 of FIG. 2. As seen, the structure 302 includes a shift register 304 coupled to TDI and TDO for shifting data, and an update register 306 coupled to the parallel outputs of the shift register for updating data from the shift register. If FIG. 3 is seen to represent IR 206, the shift register 304 will shift data from TDI to TDO in response to the Tap controller being in the Shift-IR state 1210 of FIG. 12. Following the shift operation, the Tap controller will output an UpdateDR signal 308, in the Update-IR state 1212 of FIG. 12, to cause the update register 306 to parallel load the data shifted into the shift register. If FIG. 3 is seen to represent DR 208, the shift register 304 will shift data from TDI to TDO in response to the Tap controller being in the Shift-DR state 1214 of FIG. 12. Following the shift operation, the Tap controller will output an UpdateDR signal 308, in the Update-DR state 1216 of FIG. 12, to cause the update register 306 to parallel load the data shifted into the shift register. If seen as a DR, bus outputs 310 and 312 represent bus 212 of FIG. 2. If seen as an IR, bus outputs 310 and 312 represent bus 214 of FIG. 2. Bus 310 is the normal update output bus from the update register. Bus 312 is a bus output from the shift register. The use of bus 312 by the present disclosure will be described later in regard to FIG. 11.
FIG. 4 is provided to simply show that TDS 104 can be positioned before Tap domain circuit block 106 if desired. The TDS still operates the same to select Tap domains in circuit block 106, it is just repositioned in the IC's TDI to TDO scan path.
FIG. 5 illustrates an example 502 where four ICs 102 are connected together serially from TDI 504 to TDO 506 on a board or other substrate. This example illustrates use of referenced U.S. Pat. No. 7,058,862. Each IC 102 is also connected to TCK, TMS, and TRST 508 control inputs on the board or other substrate. In this arrangement, each IC's internal Tap domains in circuit block 106 can be selected, via each IC's TDS 104, to be included in or excluded from the TDI 504 to TDO 506 scan path. For clarification, one TAP domain 202 comprising an IR 206 and a DR 208 is shown being selected within each IC's TAP domain circuit block 106 of arrangement 502. As seen, the TDS's of each IC 102 are always included in the scan path from TDI 504 to TDO 506. Maintaining the TDS's in the TDI 504 and TDO 506 scan path after they have served their purpose of selecting Tap domains hinders the optimization of serial test, debug, emulation, and/or programming operations. For example, during test, debug, emulation, and/or programming operations, 1149.1 instruction scan operations to IRs 208 and data scan operations to DRs 208 may be used intensely. Having to pad the instruction and data scan patterns with the additional bits required to traverse the TDS's IR 206 and DR 208 scan paths extends the scan pattern length beyond that of the selected Tap domain's IR 206 and DR 208. Also it requires editing each individual instruction and data scan pattern transmitted from TDI 504 to TDO 506 to insert the padding bits for the TDS circuit's IR 206 and DR 208.
It is therefore desirous to provide a method of removing TDS circuits from a TDI to TDO scan path after they have been used to select Tap domains and to provide a method of replacing TDS circuits back into a TDI to TDO scan path when it is necessary to again access them to select a new group of Tap domains for access in a TDI to TDO scan path. It is an object of the present disclosure that the removal of TDS circuits from the TDI to TDO scan path be achieved using only the IC's IEEE 1149.1 interface signal leads. It is also an object of the present disclosure that the replacement of TDS circuits back into the TDI to TDO scan chain be achieved using only the IC's IEEE 1149.1 interface signals and without having to:    1. reset the Tap domain test logic in an IC by activating the TRST input or by cycling the Tap controller of the Tap domains into the Test Logic Reset state using the TMS input,    2. cycle power to the ICs,    3. in any way alter or lose any stored state information in the ICs functional and Tap domain test circuitry, or    4. disturb the state of any legacy Tap domains of ICs in the scan path that do not use the Tap domain selection architecture of FIG. 1 or 4.